Arcade Machine Games

Operator Panel

• Weight Loss Plan That Is Sure To Work

ZAXXON is a microprocessor based, digital-integrated circuit computer video game. The heart of the computer is the CPU (U24), a Z80A located on the 834-0214 Assy IC Board A. The Alpha type chip MUST ALWAYS be used, as the Z80 is not fast enough to run the programs.

Master timing is crystal-driven at 48.66 MHz, (XI, Zone 6-D, Sht. 7, Assy. IC Bd. B, 834-0211) through Ql, Q2, Tl, U19, U38, U41, and frequency dividers Ul, U2, and U21. CPU timing (1H) is taken from U1 p-14, through U45, U9, applied to Bus Driver U94 p-6 (Zone 8-D, Sht. 8, Assy. IC Bd. B, 834-0211), through P3 p-9 to the "A"Board (Zone 1-A, Sht. 14, Assy. IC Bd, A, 834-0214) is referenced by U25 and 014 (Zone 8-D, Sht. 14, Assy. IC Bd, A, 834-0214) and finally applied to pin-6 of the CPU (U24). Back at U45 (Zone 4-A, Sht. 7, Assy. IC Bd. B, 834-0211) the ÏH pulse is used to clock the Octal Flip-Flops U16 and U25 (Sht. 6, 834-0211).

Manual system reset comes from the operator panel through P5 p-L, appears as a LO at U53 p-1 (Zone 4-D, Sht. 13, Assy. IC Bd. A, 834-0214) and is then felt at pin-26 of the CPU (Zone 8-C, Sht. 14, 834-0214). Normal program interrupts (INT) are felt at pin-16 of the Z80A (an edge-triggered LO), and are the result of Input/Output activity times with vertical blanking (an approx. 2 msec, instruction interrupt). The WAIT signal is used to synchronize that I/O activity during an interrupt to the CPU. U33 (Zone 6-D, Sht. 14, Assy. IC Bd. A) is an address bus controller. Three of the sixteen address lines pass through U33 and subsequently drive the Chip Enable inputs of ROMs 1, 2, and 3 (U27, U28, and U29), and RAMs U37 and U38. U81, U82, U86, U87 9 and U88 (Sht. 13, Assy. IC Bd. A, 834-0214) are input ports on the data bus. Connector P5 supplies player input information, CPU reset, service switch, game start and coinage to the input ports. U101, U66, U84, and U51 input COIN B, and U101, U65, U84, and U89 input COIN A, together with Player 1 and 2 start, to data bus buffer U88. U82 accesses/buffers Player 1 and 2 Left/Right data, U81 buffers Player 1 and 2 Up/Down data, U86 buffers Player 1 and 2 fire data, and U87 serves for Option Selection data. SW3 is the self-test switch. When closed, it applies a 10 to pin-17 (NMI) of the Z80A, initiating a systems/function verification as follows:

ZAXXON Self-Test

1. ROM Test

Both results are displayed simultaneously.

2. Work RAM Test

ROM TEST ROM 1 OK or N6 ROM 2 OK or N6 ROM 3 OK or NG RAM TEST RAM I OK or NG RAM 2 OK or NG

- The ROM Test sum-check is made for the 3K bytes which contain a part of this test program, out of 4K bytes in ROM 1 (2532), and for ROM 2 and 3 (2564). The sum-check adds each byte of each ROM, retains only the last 16 bits (hexadecimal 4 digits), and compares this value with the value stored in ROM 1.

- The Work RAM Test is made for two Work RAMs (2K bytes each). Each RAM is loaded with the hexidecimal "55", reads 1 byte at a time, and checks if it is a hexadecimal "55", repeating this process with the hexadecimal "A". This test is made to check interference between adjacent bits. * - Press the PLAYER 1 START BUTTON to advance the test step. Scroll Screen Test